The present invention relates to correcting clock phases, and more specifically, to using a quadrature phase corrector that includes differential amplifiers for adjusting phase shifts between clock signals.
In source-synchronous communication systems, a transmitter sends a clock signal along with data signals. A receiver uses the received clock signal to detect (or read) the data in the data signals signal. In non-source-synchronous communication systems, the transmitter sends only the data signals to the receiver. Using clock data recovery, the receiver generates a clock that is then used to detect the data in the received data signals.
Regardless whether the communication system is source-synchronous or non-source-synchronous, the receiver may need to adjust the phase of the clock before reading the data. For example, skew or noise may cause the clock signal and the data signals to be misaligned. To detect the data, the receiver phase shifts the clock signal so that the rising edge of the clock signal is in the middle of the data signal eye (or unit interval). To do so, the receiver typically includes a phase locked loop (PLL) for phase shifting the clock signal; however, the PLL introduces a long delay and can lead to unstable results.